Hardware Implementation of Fir Filter Based on Number-theoretic Fast Fourier Transform in Residue Number System
V.M. Amerbaev, R.A. Soloviev, D.V. Telpukhov*Institute for Design Problems in Microelectronics of RAS, Zelenograd, Moscow
Abstract
New approach to hardware FIR filter implementation is described in this paper. Method includes the conversion
to the frequency domain, as well as the principles of residue number systems and number-theoretic transforms. Parameterized
RTL IP-core generators were implemented for both conventional and developed methods. These IP generators
were used to implement different devices for different filter orders and input widths. Filters were synthesized, and resulting
time and hardware evaluation allow one to consider the effectiveness of the method compared with the conventional
realization of FIR filter.
Keywords: Convolution theorem, finite impulse response filter, number theoretic fast fourier transform, residue number system, verilog.
Article Information
Article History:
Received Date: 20/03/2014
Revision Received Date: 25/06/2014
Acceptance Date: 02/07/2014
Electronic publication date: 12/11/2014
Collection year: 2014
© Amerbaev et al.; Licensee Bentham Open.
open-access license: This is an open access article licensed under the terms of the Creative Commons Attribution Non-Commercial License (
http://creativecommons.org/licenses/by-nc/3.0/) which permits unrestricted, non-commercial use, distribution and reproduction in any medium, provided the work is properly cited.
* *Address correspondence to this author at the Institute for Design Problems in Microelectronics of RAS, Zelenograd, Moscow; Tel: 8(499)7299890;
Fax: 8(499)7299208; E-mail: nofrost@inbox.ru
Open Peer Review Details |
Manuscript submitted on 20-03-2014 |
Original Manuscript |
Hardware Implementation of Fir Filter Based on Number-theoretic Fast Fourier Transform in Residue Number System |