| Existing Implementations | Proposed Implementations | ||||
|---|---|---|---|---|---|
| Multiplier Design | FPGA Chip | FMax (MHz) / Delay (ns) | Multiplier Design | FPGA Chip | FMax (MHz)/ Delay (ns) |
| 8-BIT CLA MUL [22] (2015) | Spartan 3E | NA/29.4 ns | 8-BIT SEQ_MUL_CSA | Kintex-7 (xc7k480t-3ffg1156) |
710.227 MHz/ 4.572 ns |
| 8-BIT Radix-4 Booth MUL [26] (2011) | Vertix2 (xc2vpx70-7-ff1704) |
191.5 MHz/ 5.22 ns | |||
| 8-BIT Radix-8 Booth MUL [27] (2014) | Spartan 3 | NA/24.6 ns | |||
| 8-BIT Array MUL [28] (2013) | Virtex-5 (using dsp48e) |
NA/5.6 ns | |||
| 8-BIT Vedic MUL [29] (2014) | Spartan 6 (xc6slx75t-3fgg676) |
NA/15.7 ns | |||
| 32-BIT SEQ MUL [23] (2012) | xis2 -chip | NA/9.0 ns | 32-BIT SEQ_MUL_CSA | 515.31 MHz/ 8.276 ns |
|
| 32-BIT Booth MUL [24] (2013) | Spartan 3 | NA/81.8 ns | |||
| 32-BIT Wallace Tree MUL [25] (2012) | Vertix6 low power (xc6vlx75tl-1lff484) |
NA/9.536 ns | |||
| 512-BIT Mont MUL [30] (2014) | Altera Cyclone IV (ep4ce115f29c7) |
239.8MHz/NA | 512-BIT SEQ_MUL_CSA | 330.9MHz/ 18.132ns |
|