The Open Cybernetics & Systemics Journal




(Discontinued)

ISSN: 1874-110X ― Volume 12, 2018
RESEARCH ARTICLE

Fast Radix-2 Sequential Multiplier Using Kintex-7 FPGA Chip Family



Qasem Abu Al-Haija1, *, Sharifah M. S. Ahmad2
1 Department of Electrical Engineering, King Faisal University, Ahsa, 31982, P. O. 380, Saudi Arabia
2 Faculty of Engineering, Universiti Putra Malaysia 43400, UPM, Serdang, Selangor, Malaysia

Abstract

Subheading:

Benchmarking of Radix-2 Sequential Multiplication using five Xilinx FPGA families.

Background:

This paper presents description on the implementation of fast radix-2 sequential multiplier using repeated carry save addition (CSA) method with variable data path sizes ranging from 8 bits to 1024 bit.

Objective:

The main objective of this paper is to achieve the best achievable time delay reduction with better performance (i.e. frequency) running on FPGA platforms and prove their applicability in high performance reconfigurable computing.

Methods:

The design was implemented using VHDL description language and synthesized using five different Xilinx FPGA chip families, namely: vertix7, kintex7, artix7, zynq7 and spartan6. Rigorous tests were conducted and analyzed in terms of maximum frequency and total delay time of the FPGA design as well as the hardware utilization.

Results:

The results on the code synthesizing demonstrated that the proposed 1024-bit sequential multiplier with kintex7 chip family outperforms others with a maximum frequency of 296 MHz, while Spartan 6 recorded the lowest frequency with 140 MHz.

Conclusion:

The performance of the proposed multiplier-based CSA was benchmarked against other state-of-the-art designs which results reflected its superiority in terms of throughput of two or more multiple times as compared to others.

Keywords: Adder , Coprocessors , Integrated circuit synthesis , field programmable analog arrays , Digital arithmetic , Sequential multiplication, Hardware description language (HDL) .

Article Information


Identifiers and Pagination:

Year: 2018
Volume: 12
First Page: 30
Last Page: 41
Publisher Id: TOCSJ-12-30
DOI: 10.2174/1874110X01812010030

Article History:

Received Date: 12/09/2017
Revision Received Date: 12/02/2018
Acceptance Date: 13/02/2018
Electronic publication date: 09/03/2018
Collection year: 2018

© 2018 Abu Al-Haija and Ahmad.

open-access license: This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 International Public License (CC-BY 4.0), a copy of which is available at: (https://creativecommons.org/licenses/by/4.0/legalcode). This license permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.


* Address correspondence to this author at the Department Electrical Engineering, King Faisal University, Ahsa, 31982, P. O. 380, Saudi Arabia; Tel; +966135895400; E-mails: Qalhaija@kfu.edu.sa, Eng_Qasem1982@Yahoo.com


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