Institute for Design Problems in Microelectronics of RAS, Zelenograd, Moscow
New approach to hardware FIR filter implementation is described in this paper. Method includes the conversion
to the frequency domain, as well as the principles of residue number systems and number-theoretic transforms. Parameterized
RTL IP-core generators were implemented for both conventional and developed methods. These IP generators
were used to implement different devices for different filter orders and input widths. Filters were synthesized, and resulting
time and hardware evaluation allow one to consider the effectiveness of the method compared with the conventional
realization of FIR filter.
Keywords: Convolution theorem, finite impulse response filter, number theoretic fast fourier transform, residue number system, verilog.
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