Abstract HTML Views: 391 PDF Downloads: 235 Total Views/Downloads: 626
Abstract HTML Views: 239 PDF Downloads: 159 Total Views/Downloads: 398
Functional verification has become a major challenge in the chip design area. To improve the efficiency of
verification, it is necessary to choose appropriate verification method and tools. An important aspect of functional
verification is RTL verification, simulation-based verification is main method in RTL verification. Based on FT-8 multicore
processor, we developed a configurable test stimulus acceleration method, loading the test stimulus into memory and
L2 cache to speed up the processor instructions fetch, which can shorten simulation cycle and simulation time, reduce the
verification cost and guaranteed the correctness of design.